4T CMOS NAND — Two inputs, one output

A CMOS NAND with four transistors and two interconnect layers. This local project preserves its recorded creation, audit, and revisions.

공정 개요

P-type Si substrate: upper region
Prepare the upper observation region of the P-type Si substrate. The NMOS body and p+ body tap connect through this region. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Form the PMOS n-well
Convert the upper 140 nm of the PMOS region into an n-type well. Leave the p-type substrate underneath to form the well–substrate junction. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Protect Active regions and body taps
Protect the black mask shapes with photoresist and open the surrounding area. The resist shields the protected regions during the following etch. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Etch the STI trenches
Remove 80 nm of Si between the Active regions and taps. Preserve continuous body and well paths beneath the trenches. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Strip resist and clean
Remove the resist after pattern transfer and prepare the surface for the next deposition or doping step. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Fill STI with oxide
Fill the spaces between raised features with SiO₂ to provide insulation for subsequent processing. This is a geometric representation of bulk CVD fill; the following CMP sets the target plane. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Planarize STI to the Active surface
Remove excess oxide to align the STI surface with the Si Active regions, providing a planar starting surface for Gate formation. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Grow Gate SiO₂
Grow Gate oxide on exposed Si. Retain an insulating layer beneath each Gate rather than an electrical contact. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Deposit the Poly-Si Gate film
Deposit a Poly-Si film. Subsequent patterning and selective doping form the four Gate electrodes. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Pattern resist for four Gates
Protect the black mask shapes with photoresist and open the surrounding area. The resist shields the protected regions during the following etch. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Separate the four Poly-Si Gates
Remove unprotected Poly-Si. Two Gates remain on each of the lower and upper diffusion strips. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Open the Source/Drain oxide
Use the Gate resist and Poly-Si as shields while removing the surrounding oxide. Retain the Gate dielectric and expose the junction surfaces for doping. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Strip resist and clean
Remove the resist after pattern transfer and prepare the surface for the next deposition or doping step. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Form shallow N-type junctions
Form shallow Source/Drain extensions in the exposed Si before spacer formation. Each Gate shields the channel center so that the junctions on opposite sides remain separated. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Complete shallow N-type junction formation
Form shallow Source/Drain extensions in the exposed Si before spacer formation. Each Gate shields the channel center so that the junctions on opposite sides remain separated. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Form shallow P-type junctions
Form shallow Source/Drain extensions in the exposed Si before spacer formation. Each Gate shields the channel center so that the junctions on opposite sides remain separated. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Complete shallow P-type junction formation
Form shallow Source/Drain extensions in the exposed Si before spacer formation. Each Gate shields the channel center so that the junctions on opposite sides remain separated. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Deposit the Si₃N₄ spacer liner
Coat the Gate sidewalls and horizontal surfaces with nitride. The sidewall film remaining after directional etching offsets the deep junctions from the Gate. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Etch back the nitride spacer film
Remove horizontal nitride while retaining Gate sidewall spacers. The spacers protect part of the shallow extension regions. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Dope the N-type Source/Drain and Gates
Dope the exposed Source/Drain regions to greater depth and dope the full Poly-Si Gate thickness. The substrate or well tap under the same selection mask also becomes a heavily doped contact region. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Complete N-type Source/Drain and Gate doping
Dope the exposed Source/Drain regions to greater depth and dope the full Poly-Si Gate thickness. The substrate or well tap under the same selection mask also becomes a heavily doped contact region. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Dope the P-type Source/Drain and Gates
Dope the exposed Source/Drain regions to greater depth and dope the full Poly-Si Gate thickness. The substrate or well tap under the same selection mask also becomes a heavily doped contact region. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Complete P-type Source/Drain and Gate doping
Dope the exposed Source/Drain regions to greater depth and dope the full Poly-Si Gate thickness. The substrate or well tap under the same selection mask also becomes a heavily doped contact region. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Fill the Contact interlayer dielectric
Fill the spaces between raised features with SiO₂ to provide insulation for subsequent processing. This is a geometric representation of bulk CVD fill; the following CMP sets the target plane. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Planarize the Contact starting surface to 400 nm
Retain dielectric above the Gates and set a common Contact starting surface at 400 nm. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Open Contact resist windows
Create resist openings at the black mask shapes, preparing to selectively remove dielectric above the intended Contact targets. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Etch Gate and junction Contact holes
Remove SiO₂ inside the Contact windows. Stop selectively at the Poly-Si and Si junction surfaces, which lie at different heights. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Strip resist and clean
Remove the resist after pattern transfer and prepare the surface for the next deposition or doping step. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Deposit the Contact TiN liner
Form TiN on the Contact sidewalls and bottoms as a barrier and adhesion layer between W and the surrounding materials. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Fill the W Contact plugs
Fill the interiors of Contacts and vias with W. This is a geometric representation of bulk CVD fill; the following CMP sets the target plane. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
CMP the W Contacts
Remove W and TiN from the field, leaving isolated Contact plugs in the dielectric with their top surface at 400 nm. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Deposit the Al M1 interconnect film
Deposit Al on the planar Contact surface. This layer forms the two inputs, supply connections, and output landings. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Protect the M1 pattern
Protect the black mask shapes with photoresist and open the surrounding area. The resist shields the protected regions during the following etch. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Separate M1 external nets and output landings
Remove Al between the resist features. A, B, VDD, VSS, and the output landings must remain separated. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Strip resist and clean
Remove the resist after pattern transfer and prepare the surface for the next deposition or doping step. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Fill the dielectric above M1
Fill the spaces between raised features with SiO₂ to provide insulation for subsequent processing. This is a geometric representation of bulk CVD fill; the following CMP sets the target plane. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
Planarize the M2 starting surface to 520 nm
Leave an 80 nm dielectric separation above M1 and set the via starting surface at 520 nm. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Open the output vias
Create resist openings at the black mask shapes, preparing to selectively remove dielectric above the intended Contact targets. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Etch the output V1 holes
Remove oxide above the two M1 output landings. Preserve the Al landings at the via bottoms. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Strip resist and clean
Remove the resist after pattern transfer and prepare the surface for the next deposition or doping step. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
V1 TiN liner
Line the via bottoms and sidewalls with TiN in preparation for W plug fill. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Fill the W V1 plugs
Fill the interiors of Contacts and vias with W. This is a geometric representation of bulk CVD fill; the following CMP sets the target plane. [Intel Technology Journal 6(2), 130nm Logic Technology, Fig. 7–8 (2002)](https://www.intel.com/content/dam/www/public/us/en/documents/research/2002-vol06-iss-2-intel-technology-journal.pdf)
CMP the via plugs
Remove field W and TiN, leaving two V1 plugs at the 520 nm plane. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Deposit the Al M2 output film
Form an Al output interconnect film on the planar via surface. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Protect the output Y interconnect
Protect the black mask shapes with photoresist and open the surrounding area. The resist shields the protected regions during the following etch. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Pattern the M2 output Y
Retain only the Al connecting the two output vias and the Y pin on the right. Dielectric separates it from inputs A and B below. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)
Strip resist and clean
Remove the resist after pattern transfer and prepare the surface for the next deposition or doping step. [A. Mason, MSU ECE 410, Ch. 3–5, pp. 3.20–3.22, 3.28–3.35, 3.56](https://www.egr.msu.edu/classes/ece410/mason/files/Ch3-5.pdf)

저장된 공정 단계: 47

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These providers may process information outside your country. The primary Supabase processing region currently configured for Arpelier is Southeast Asia (Singapore). Processing locations and providers may change as infrastructure changes, and material changes will be reflected in this Policy.

5. Retention and Deletion

Arpelier keeps information only for as long as reasonably needed for the purposes in this Policy. The period depends on the type of information, whether an account or project remains active, operational and security needs, user requests, disputes, and legal requirements.

A project owner can delete an individual project through the Service.
Account deletion and related data deletion may be requested at contact@arpelier.com. The current Service does not provide a self-service account-deletion control.
Support records and service logs are kept for as long as reasonably needed to respond, operate, secure, improve, and handle related disputes or legal duties.
A process flow sent to the AI connector is not kept after its result is returned. Calculated structures derived from it are kept for up to one hour, as described in section 1, and then deleted automatically. A link you ask for keeps the project made from the flow, with its calculated structure when included, for 7 days and is then deleted automatically; a project someone saves from it is kept like any other project. Only the operational request logs described above remain with the hosting provider for its retention period.

Deletion may take additional time in provider systems, residual copies, or records that must be retained by law. Arpelier does not promise a fixed backup or residual-copy deletion schedule. Information retained for legal or security reasons is separated or restricted where reasonably appropriate and deleted when that need ends.

6. Security

Arpelier applies reasonable administrative and technical safeguards, including access controls that distinguish owners, invited collaborators, public access, and authorized operators.

No internet-based service can guarantee absolute security. If a security incident or data loss is confirmed, Arpelier will investigate and take reasonable steps to contain the issue, reduce harm, and provide notices required by applicable law.

Arpelier does not sell personal information and does not disclose it for third-party advertising or ad targeting.

Information may be disclosed to the service providers above, at a user’s direction, to protect the Service and its users, or where required by law. Public project content is disclosed according to the visibility settings selected by its owner.

8. Your Rights

Subject to applicable law, users may request access to, correction or deletion of, or restriction of processing of their personal information, and may request account deletion. Arpelier may need to verify the requester’s identity and may retain information where law permits or requires it.

Send requests to contact@arpelier.com.

9. Changes to This Policy

We may update this Policy to reflect changes in law, the Service, or our providers. The effective date will be shown on this page, and material changes will be announced within the Service or through another reasonable channel.

Change history: November 10, 2026 — the AI connector may keep calculated structures for up to one hour so that long calculations can continue, and can make a link, kept for 7 days, that opens a result in Arpelier (sections 1, 4 and 5). November 9, 2026 — added “AI connector requests” to section 1 and the AI connector item to section 5. The version before these took effect on August 5, 2026.

10. Contact

For privacy questions or requests, contact Arpelier at contact@arpelier.com.

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Terms & Privacy

At a Glance

Terms of Service

1. Purpose and Scope

2. Our Commitments

3. Using the Service and Guest Access

4. Accounts and Security

5. User Content and Ownership

6. Project Visibility and Sharing

7. Sensitive Information and Organizational Policies

8. Technical Results and Appropriate Use

9. Prohibited Conduct

10. Service Changes, Suspension, and Discontinuation

11. Limitation of Liability

12. Changes to These Terms

13. Contact and Governing Law

Privacy Policy

1. Information We Collect

2. How We Use Information

3. Project Data and Operator Access

4. Service Providers and International Processing

5. Retention and Deletion

6. Security

7. Sharing and Sale of Information

8. Your Rights

9. Changes to This Policy

10. Contact