Arpelier

Arpelier is a web-based, process-driven visualization tool that turns semiconductor and microfabrication process flows into step-by-step 3D structures and cross-sections. When a process order or condition changes, affected downstream structures are recalculated and reflected in the view. It is built for structural understanding, education, early idea exploration, review, and communication—not as a replacement for professional TCAD or process validation.

Last reviewed August 5, 2026

From process input to structural output

You describe a structure through its process history: the ordered flow, conditions for each step, materials, and masks. Arpelier applies those inputs in sequence and keeps the resulting structure connected to the point in the flow that created it.

You provide

Process steps and their order
Geometric and process conditions
Materials
Masks and patterns

Arpelier produces

A 3D structure at each process stage
X, Y, and Z two-dimensional cross-sections
A three-dimensional cutaway within a selected range
A sequence that can be inspected, captured, and shared

Process-driven rather than general-purpose CAD

General 3D CAD begins with geometry that a user draws or assembles directly. Arpelier begins with a process flow. Deposition, lithography, etching, implantation, planarization, and other supported operations change the current structure in sequence, so the geometry can be read together with how it was formed.

If an earlier order or condition changes, Arpelier recalculates the affected later stages and reflects the result in the viewer in real time. This makes it easier to ask both “what does the structure look like?” and “which process step made it look that way?”

Who Arpelier is for

Students can connect unit-process concepts with structural evolution. Educators can prepare structures and sequences for teaching. Researchers and engineering teams can visualize an early process idea, review it with colleagues, and communicate fabrication flow in a presentation. The use cases page describes these workflows in detail.

Anyone, easily, quickly, and together

Arpelier is guided by a simple principle: semiconductor technology can remain technically deep while the act of inspecting, understanding, and explaining a structure becomes more approachable. Official examples provide a starting point, and project links, QR sharing, and public projects make it possible to examine and discuss structures with other people.

Scope and limits

Arpelier focuses on geometric process–structure relationships. It does not primarily predict electrical device characteristics, guarantee equipment-recipe outcomes, reproduce every material or physical phenomenon, or guarantee fabrication results and yield. Professional TCAD, experiments, and process validation remain necessary when those questions matter.

See Arpelier vs TCAD for the detailed boundary and how the two roles can complement each other.

Official

Official examples are public projects prepared by Arpelier for people who are beginning to explore the relationship between process and structure. Each example includes an ordered flow, process conditions, materials, masks, and stage-by-stage 3D structures, so you can inspect how a process changes geometry without first building a project from an empty workspace.

The current set spans planar MOSFET isolation, gate, source/drain, and contact formation; a crossbar built from orthogonal routing layers; vertical-memory structures involving channel holes, staircases, replacement gates, and floating gates; a 6F² DRAM cell arrangement with diagonal active regions and shared contacts; and a metal hierarchy extending from LI/M0 to an M7 power grid. Together they present different structural problems for comparison rather than prescribing one correct fabrication flow.

Opening a card below takes you to the corresponding Arpelier project. Move backward and forward through its process stages, rotate the structure, and inspect cross-sections to see how intermediate geometry accumulates. These examples are starting points for learning and exploration; they are not equipment recipes or qualified production flows.

Official

Simple MOSFET

Trace source, gate, drain, and the p+ body tap through contacts into three isolated first-metal routes.

Official

3D VNAND (SONOS)

A 3D VNAND SONOS flow covering the mold, staircase, channel hole, replacement gates, and metal.

Official

6F² DRAM Cell Supercell

A conceptual four-cell 6F² DRAM motif with diagonal active islands and shared bit-line contacts.

Official

Simple Crossbar

Inspect nine isolated storage cells at the crossings of three word lines and three bit lines.